1. Field of the Invention
This invention relates to a semiconductor integrated circuit, especially to the semiconductor integrated circuit with a high voltage reception terminal to which a positive high voltage that is higher than the power source voltage or a negative high voltage that is lower than the ground voltage is applied.
2. Description of the Related Art
A high voltage reception terminal, to which a positive high voltage that is higher than the power source voltage is applied, has been formed in a semiconductor integrated circuit such as micro computer. FIG. 5 shows the circuit diagram of the semiconductor integrated circuit with the high voltage reception terminal. When the power source voltage VDD of the semiconductor integrated circuit is 5V, an input voltage of 0-12V is applied to the high voltage reception terminal 50. A CMOS inverter 52 (input buffer) is connected to the high voltage reception terminal 50 though an input resistor 51. The CMOS inverter 52 includes a P channel type MOS transistor (refereed to as the PMOS hereinafter) (T1) and an N channel type MOS transistor (referred to as the NMOS hereinafter) (T2) and the gates of these transistors receive an input voltage coming from the high voltage reception terminal 50. An output transistor 53, which is a high withstand voltage transistor NMOS (T3), is also connected to the high voltage reception terminal 50. When the output transistor 53 is used, the voltage of 0-12V also appears in the high voltage reception terminal 50.
The withstand voltage of the gates of the PMOS (T1) and the NMOS (2) of the CMOS inverter 52 is set higher than 12V and the withstand voltage of the drain of the NMOS (T3) of the output transistor 53 is also set higher than 12V.
The gate insulation film is formed thicker than the MOS transistor supplied with the power source voltage VDD (VDD=5V) in order to secure the withstand voltage of the gate of the PMOS (T1) and the NMOS (T2). However, when the gate insulation film is thicker, the threshold voltage Vt goes up, leading to the smaller margin of the input voltage range of the CMOS inverter 52 when the power source voltage VDD is low.
Therefore, the manufacturing process of ion doping for adjusting the threshold voltage is added in order to lower the Vt of the PMOS (T1) and the NMOS (T2).
The input-output circuit of the semiconductor integrated circuit is described in Japanese Patent Application Publication Nos. H09-093115 and H09-172146.
However, the number of manufacturing processes increases, when the process of ion doping for adjusting the threshold voltage for lowering the Vt of the PMOS (T1) and the NMOS (T2) is added, leading to the higher manufacturing cost.